4.3.2.2 Design Layout Recommendations

When designing the Ethernet interface, consider the following recommendations:

• ETH_TX_P, ETH_TX_N, ETH_RX_P and ETH_RX_N should be routed on the top layer without any vias. Traces must be straight.
• ETH_TX_P and ETH_TX_N should be matched in length to within 120 mils.
• ETH_RX_P and ETH_RX_N should be matched in length to within 120 mils.
• ETH_TX_x and ETH_RX_x must be symmetric.
• Place the TX_P and TX_N signals at least 2 times the trace width away from other signals for noise immunity.
• Place signals at least 2 times the trace width away from any copper plan.
• Place the TX and RX signals at least 5 times the trace width away from other signals for noise immunity.
• Check that the ETH_TX_x and ETH_RX_x line impedance is the same for all signal layers. Recommended differential impedance for net: 100Ω ± 5%.