4.1.3 Power Management Unit

The MCP16502 is a full-featured Power Management Integrated Circuit (PMIC), cost- and size-optimized for Microchip MPU devices.

The Microchip SAMA5D27 SOM is supplied by an external 5V supply (VDD_MAIN) and generates its own internal supplies by interfacing with the Microchip MCP16502 Power Management Unit.

The MCP16502 integrates four DC-DC buck regulators used for system supplying and two auxiliary LDOs for customer purposes.

All buck channels can support loads up to 1A. All bucks are 100% duty cycle capable.
- DCDC1 set @ 3.3 V supplies all pads of the embedded devices. This power rail offers a 600-mA load to customer applications through pins 12 and 13 (VDD_3V3).
- DCDC2 set @ 1.2V supplies the LPDDR2 I/O memory. It is used internally only.
- DCDC3 set @ 1.2V supplies the core of the microcontroller. It is used internally only.
- DCDC4 set @ 1.8V supplies the LPDDR2 Core memory. It is used internally only.
One 300 mA LDO set @ 3.3V internally is provided to supply Radio Power Amplifier of the ATWILC3000 module.
One 300 mA LDO is provided so that sensitive analog loads can be supported. The LDO output voltage, named VLDO2 (accessible through pin 180), is disabled by default at power-up. Output voltage values are set through an I²C interface access after system initialization.

The default power channel sequencing is built-in, according to the requirements of the Microchip MPU device.

The MCP16502 features a low no-load operational quiescent current, and draws less than 10 uA in full shutdown.

Active discharge resistors are provided on each output. All buck channels support safe start-up into pre-biased outputs.

The MCP16502 is available in a 32-pin 5 mm x 5 mm VQFN package with an operating junction temperature range from –40°C to +125°C. It is AEC-Q100 Grade 2 (T_AMB=105°C) qualified.

The LPM pin of the Microchip SAMA5D27 System-On-Module, combined with HPM and PWRHLD (also named SHDN) pin status of the MCP16502 PMIC, define different power states which are illustrated in the table below.

Note: HPM is forced to “0” by hardware, since the high-performance feature of the MCP16502 PMIC is not supported by the SAMA5D27 SIP MPU device. For more information, refer to the MCP16502 data sheet (see Reference Documents).

Table 4-1. MCP16502 Default Power States
PWRHLD	LPM	Buck1	Buck2	Buck3	Buck4	LDO1	LDO2	nRST	Power State ⁽¹⁾
0	0	Off	Off	Off	Off	Off	Off	Low	Off
0	1	Off	On⁽²⁾	Off	On⁽²⁾	Off	Off	Low	Hibernate mode
1	1	On⁽²⁾	On⁽²⁾	On⁽²⁾	On⁽²⁾	On	Off	HiZ	Low-Power mode
1	0	On⁽³⁾	On⁽³⁾	On⁽³⁾	On⁽³⁾	On	Off	HiZ	Active mode

Note:

Only allowed modes are listed. If the PWRHLD/LPM/HPM combination is not listed, then the mode is not allowed.
In this mode, the DCDC is configured in Automatic Pulse-Frequency Modulation (Auto-PFM) mode.
In this mode, the DCDC is configured in Force Pulse-Width Modulation (FPWM) mode.

For more information about the use of the MCP16502 PMIC LPM feature, refer to the MCP16502 data sheet (see Reference Documents).

The LPM pin is controlled internally by PIOBU0 pin, as shown in the figure below.

Figure 4-1. PIOBU0 PMIC