4.2.3.1 LPDDR2 Power-Off Sequence

The LPDDR2 power-off sequence must be controlled by software to preserve the LPDDR2 device.

In this sequence, the CKE signal should be low during the full period the power rails are powering down.

The power failure can be controlled by the embedded Voltage Supervisor (MIC842) and handled at system level (IRQ on PD31). The LPDDR2 power-off sequence is applied using the bit LPDDR2_LPDDR3_PWOFF in the MPDDRC Low-Power register (MPDDRC_LPR).

For more information, refer to the following documents:

• SAMA5D2 Series Data sheet available on www.microchip.com/, sections LPDDR2 Power Fail Management and MPDDRC Low-Power Register
• Jedec Standard Low Power Double Data Rate 2 (LPDDR2), JESD209-2B