4.6 Initialization
When the device is in a reset state, the IRQ_N interrupt pin is high-impedance and will be pulled high through an external pull-up resistor to VDDP. Once all device reset sources are deasserted, the device will begin its internal initialization. The device will assert the Reset Complete (RESETC) bit in the Status 2 (STS2) register to indicate that it has completed its internal initialization and is ready for configuration. As the Reset Complete status is non-maskable, the IRQ_N pin will always be asserted and driven low following a device reset. The time required for the device to initialize once all reset sources are deasserted until the IRQ_N pin is asserted, tinit, is approximately 7 μs.
At the system level, the station host controller (STA) should respond to all assertions of the IRQ_N pin with a read of critical status registers through the Serial Management Interface (SMI), including the Status 2 register. Upon reading of the Status 2 register, the pending Reset Complete status bit will be automatically cleared causing the IRQ_N pin to be released and pulled high again. The host controller may then continue to configure the device registers through the Serial Management Interface. See Figure 4-3 for an illustration of the device reset, initialization, and configuration process.
