4.4 Interrupt Management

The LAN8670/1/2 supports multiple interrupt capabilities which are not part of the IEEE 802.3 specification. An active low asynchronous interrupt signal may be generated on the IRQ_N pin when selected status events are detected as configured by the Interrupt Mask Registers.

To assert an interrupt on IRQ_N for a given event in the Status 1 (STS1) and Status 2 (STS2) registers, the corresponding mask bit in the Interrupt Mask 1 (IMASK1) and Interrupt Mask 2 (IMSK2) registers must be written to ‘0’ to enable the interrupt. When an event occurs causing the associated status bit to be set, the IRQ_N pin will also be asserted. When the event to negate the status bit is true, or the corresponding bit in the Interrupt Mask Register is set disabling the interrupt, the IRQ_N pin will be deasserted.

All PHY interrupts are disabled (masked) following a reset with the exception of the Reset Complete interrupt mask bit. The Reset Complete interrupt mask is ‘0’ by default such that the IRQ_N pin will be asserted following a reset event setting the Reset Complete status bit. This may be used to alert the station host controller that the LAN8670/1/2 has been reset and is available for configuration.