4.1 Media Independent Interface (MII)

The integrated Media Independent Interface (MII) provides a common interface between physical layer and MAC layer devices, adhering to IEEE Std 802.3-2018 IEEE Standard for Ethernet.

The MII includes the following interface signals:

  • Transmit Data - TXD[3:0]
  • Transmit Enable - TXEN
  • Transmit Clock - TXCLK
  • Transmit Error - TXER
  • Receive Data - RXD[3:0]
  • Receive Data Valid - RXDV
  • Receive Clock - RXCLK
  • Receive Error - RXER
  • Carrier Sense - CRS
  • Collision Detect - COL

In MII mode, on the transmit path, the LAN8670/2 drives the transmit clock, TXCLK, to the controller. The controller synchronizes the transmit data to the rising edge of TXCLK and drives TXEN high to indicate valid transmit data on TXD[3:0]. The device will synchronously capture TXEN, TXER, and TXD[3:0] on the falling edge of TXCLK.

On the receive path, the device drives both the receive data, RXD[3:0], and the receive clock, RXCLK. The controller captures in the receive data on the rising edge of RXCLK when the device drives RXDV high. The device drives RXER high when a receive error is detected (e.g., an uncorrectable decoding error). The device synchronizes RXD[3:0], RXDV, and RXER to change on the falling edge of RXCLK.

The CRS and COL signals are asserted asynchronously to the clocks.

For timing information, refer to the MII Timing section. Refer to Clause 22 of the IEEE Std 802.3-2018 IEEE Standard for Ethernet specification for additional MII information.

Note: Many modern controllers, often found on switches, implement a reduced pin MII assuming full-duplex point-to-point operation. These interfaces, known as MII-Lite, do not include the required CRS and COL signals for 10BASE-T1S half-duplex operation. Back-to-back connection of two half-duplex devices is also not supported due to the CRS and COL requirement.
Note: The connection of a 10 kΩ pull-down resistor on TXEN is recommended to prevent unintended transmission if the MAC does not actively pull-down or drive this pin low at all times during its reset and initialization.