4 Appendix: Supported Memory File Formats for LSRAM and μSRAM
(Ask a Question)INTEL-HEX
Intel-Hex is an industry standard file format created by Intel. File
extensions for these files are .hex
and .ihx
.
Memory contents are stored in ASCII files using hexadecimal characters. Each file contains a series of records (lines of text) delimited by new line, '\n', characters and each record starts with a ':' character. For more information about this format, see the Intel-Hex Record Format Specification.
The Intel-Hex record is composed of five fields and is arranged as:
:llaaaatt[dd...]cc
Where:
- :—start code of every Intel-Hex record.
- ll—byte count of the data field.
- aaaa—16-bit address of the beginning of the memory position for the data. Address is big Endian.
- tt—record type, defines the data field:
- 00—data record.
- 01—end of file record.
- 02—extended segment address record.
- 03—start segment address record (ignored by Microchip SoC tools).
- 04—extended linear address record.
- 05—start linear address record (ignored by Microchip SoC tools).
- [dd...]—sequence of n bytes of the data. n is equivalent to what was specified in the ll field.
- cc—checksum of count, address, and data.
Example Intel-Hex record:
:0300300002337A1E
Motorola S-Record
Motorola S-Record is an industry standard file format created by
Motorola. The file extension for these files is .s
.
This format uses ASCII files, hex characters, and records to specify memory content similar to the Intel-Hex format. See the Motorola S-record description document for more information about this format. The RAM Content Manager uses only the S1 through S3 record types. The other record types are ignored.
The major difference between Intel-Hex and Motorola-S is the record formats and extra error checking features that are incorporated into the Motorola S-record.
In both formats, memory content is specified by providing a starting address and a data set. The upper bits of the data set are loaded into the starting address and leftovers overflow into the adjacent addresses until the entire data set has been used.
The Motorola S-record is composed of six fields and arranged as follows:
Stllaaaa[dd...]cc
Where:
- S—start code of every Motorola S-record.
- t—record type, defines the data field.
- ll—byte count of the data field.
- aaaa—16-bit address at the beginning of the memory position for the data. Address is big Endian.
- [dd...]—sequence of n bytes of the data; n is equivalent to what was specified in the ll field.
- cc—checksum of count, address, and data.
S10a0000112233445566778899FFFA
Simple-Hex
Simple-Hex is a format created by Autodesk. SHX files are used for environment enabling
designs of 2D and 3D projects for engineering purposes. These files end with an SHX
extension (for example, file2.shx
or file3.shx
).
The Simple-Hex record is arranged as follows:
0:2000D9B8
Where, the colon (:
) separates the address from the data.
Binary
Binary files consist of a sequence of bytes, with the binary digits (bits) grouped in
eights. Files consist of 0s and 1s and end with a BIN extension. For example,
file2.bin
or file3.bin
.
The Binary record is composed as follows:
001100101010101010010010
MEMFILE (RAM Content Manager output file)
Transfer of RAM data (from the RAM Content Manager) to test equipment is accomplished through MEM files.
The contents of RAM is first organized into the logical layer and then reorganized to
fit the hardware layer. Then it is stored in MEM files that are read by other systems
and used for testing. The MEM files are named according to the logical structure of the
RAM elements created by the configurator. In this scheme, the highest order RAM blocks
are named CORE_R0C0.mem
, where R
stands for row and
C
stands for column. For multiple RAM blocks, the naming continues
with CORE_R0C1
, CORE_R0C2
, CORE_R1C0
,
and so on.
The data intended for the RAM is stored as ASCII 1s and 0s within the file. Each memory address occupies one line. Words from the logical layer blocks are concatenated or split in order to make them fit efficiently within the hardware blocks. If the logical layer width is less than the hardware layer, two or more logical layer words are concatenated to form one hardware layer word. In this case, the lowest bits of the hardware word are made up of the lower address data bits from the logical layer. If the logical layer width is more than the hardware layer, the words are split, placing the lower bits in lower addresses.
If the logical layer words do not fit cleanly into the hardware layer words, the most significant bit of the hardware layer words is not used and defaulted to zero. This is also done when the logical layer width is 1 in order to avoid having leftover memory at the end of the hardware block.