7 Revision History

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The revision history table describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Table 7-1. Revision History
Revision	Date	Description
H	05/2025	The following is the summary of changes in this revision of the document: Updated the document for RT PolarFire SoC support. The changes are made throughout the document. Added the Simulating ECC Errors in LSRAM section and the following sub-sections: Probability-Based ECC Flag Assertion Verilog Task-Based Flag Assertion Simulation Flow Example LSRAM Waveforms Updated Embedded Memory Blocks as follows: Added information related to the sNVM size due to the addition of built-in SECDED ECC. Added a note related to eNVM in the Embedded Memory Blocks. Updated the sNVM and eNVM for the ECC feature in Table 2-1.
G	09/2023	The following is the summary of changes in this revision of the document: Added a line on how to enable the Reset All Values option for RAM initialization. See Dual-Port Large SRAM Configurator, Two-Port LSRAM Configurator, and Memory Initialization at Power-Up. Updated the polarity and description of A_BYPASS, B_BYPASS, and ECC_BYPASS signals in Table 2-2 and Table 5-1. Updated the polarity and description of R_ADDR_BYPASS and R_DATA_BYPASS signals in Table 2-16 and Table 5-10.
F	03/2023	The following is the summary of changes in this revision of the document: Updated the document title and added RT PolarFire information. In μPROM, modified the sentence to mention that fabric logic has read-only access to µPROM. Updated ECC Mode (For x33 Two-Port Mode Only) to include information about Multi-bit errors.
E	07/2022	The following is the summary of changes in this revision of the document: Added the µPROM port BUSY, see Figure 2-33 and Table 2-18. Added sNVM storage space requirements for fabric RAM initialization, see Implementation Added MEMFILE (RAM Content Manager output file)
D	03/2022	The following is the summary of changes in this revision of the document: In Content from File, added the supported memory file formats Corrected the real value PX+QY to PX-QY in Figure 3-12 Updated Dual-Port Large SRAM Configurator and Two-Port LSRAM Configurator for describing the LSRAM behavior when the Write Byte Enables option is selected. For more information, see CN20020.
C	12/2021	The following is the summary of changes in this revision of the document: Added information about Simple-Hex and Binary memory file formats, see Appendix: Supported Memory File Formats for LSRAM and μSRAM Added Write Port Width Alignment
B	08/2021	Added MPF for PolarFire FPGA and MPFS for PolarFire SoC FPGA in Introduction.
A	08/2021	The first publication of this document. This user guide was created by merging the following documents: UG0680: PolarFire FPGA Fabric User Guide UG0912: PolarFire SoC FPGA Fabric User Guide For more information, see Table 7-2 and Table 7-3 respectively.

The following revision history table describes the changes that were implemented in the UG0680: PolarFire FPGA Fabric User Guide document. The changes are listed by revision.

Note: UG0680: PolarFire FPGA Fabric User Guide document is now obsolete and the information in the document has been migrated to PolarFire® FPGA and PolarFire SoC FPGA Fabric User Guide.

Table 7-2. Revision History of UG0680: PolarFire FPGA Fabric User Guide
Revision	Date	Description
Revision 7.0	04/2021	Updated the Read Operation in Dual-Port Mode figure to correct the output data values in the Pipeline Mode. Removed collision prevention from the LSRAM, μSRAM, μPROM, and sNVM Features table. Updated the Byte Write Enables Settings for Dual-Port Mode table 8 for 1K x 16 mode. Added information about how RAM blocks are cascaded when Write byte Enables option is selected. Updated μPROM Operation to mention that μPROM memory file supports only the plain text file. Updated the Simplified Functional Block Diagram of LSRAM in Dual-Port Mode figure and Simplified Functional Block Diagram for LSRAM in Two-Port Mode figure to show that A_BYPASS and B_BYPASS signals are control signals of the MUX. Removed Simple Write, Feed-Through Write, and Read-Before-Write specific content from two-port LSRAM. These write operations are not supported in the two-port LSRAM configuration.
Revision 6.0	04/2020	Updated information for for x33 Two-Port Mode Only in ECC mode.
Revision 5.0	04/2019	Structural changes were made throughout the document. Information about PolarFire LSRAM, μSRAM, μPROM, and sNVM Features were updated in the LSRAM, μSRAM, μPROM, and sNVM Features table. Math Block Features were updated. Libero SoC PolarFire Compile Report is moved to appendix.
Revision 4.0	03/2018	Updated the Math Blocks Resources in the Fabric Resources in PolarFire Family table.
Revision 3.0	11/2017	Revision 3.0 of this document is updated to include features and enhancements introduced in Libero SoC PolarFire v2.0.
Revision 2.0	06/2017	Added reference to the ChipPlanner user guide. Added reference to the Synplify Pro RAM block application note for LSRAM. Added reference to the Synplify Pro RAM block application note for μSRAM. Added reference to the Synplify Pro MACC block application note for MACC.
Revision 1.0	02/2017	The first publication of the document.

The following revision history table describes the changes that were implemented in the UG0912: PolarFire SoC FPGA Fabric User Guide document. The changes are listed by revision.

Note: UG0912: PolarFire SoC FPGA Fabric User Guide document is now obsolete and the information in the document has been migrated to PolarFire® FPGA and PolarFire SoC FPGA Fabric User Guide.

Table 7-3. Revision History of UG0912: PolarFire SoC FPGA Fabric User Guide
Revision	Date	Description
Revision 2.0	04/2021	Updated the Read Operation in Dual-Port Mode figure to correct the output data values in the Pipeline Mode. Removed collision prevention from the Memory Blocks table. Updated the Byte Write Enables Settings for Dual-Port Mode table for 1K x 16 mode. Added information about how RAM blocks are cascaded when Write byte Enables option is selected. Updated μPROM Operation to mention that μPROM memory file supports only the plain text file. Updated the Simplified Functional Block Diagram of LSRAM in Dual-Port Mode figure and Simplified Functional Block Diagram for LSRAM in Two-Port Mode the figure to show that A_BYPASS and B_BYPASS signals are control signals of the MUX. Removed Simple Write, Feed-Through Write, and Read-Before-Write specific content from two-port LSRAM. These write operations are not supported in the two-port LSRAM configuration.
Revision 1.0	04/2020	The first publication of the document.