3.6.3.8 Extension Adder

A Math block's adder/accumulator width can be extended using fabric logic. Figure   1 and Figure   2 show example implementations of 2-input and 3-input extension adders in fabric. In this extension adder, the MSb bits, P[47], C[47], and E[47] are not treated as sign bits. Instead, P[n-1] represents the sign bit. The static input EXT_SEL is set to 1 causing the appropriate signal to appear on each Math block's OVFL_CARRYOUT output.

The following figure shows a case where input C = 0, and input E is used for the cascade chain.

The following figure shows a case where both inputs C and E are used.