10.6 Configurations

The CHECON register controls the general configurations available for accelerating the instruction and data accesses to the Flash memory system.

The Prefetch module implements the following general options:
  • The PFMWS[3:0] bits (CHECON[3:0]) control the number of system clock cycles required to access the PFM. The total Flash Wait states is a sum of ADRWS and PFMWS.
  • The PREFEN[1:0] bits (CHECON[5:4]) control the predictive and prefetched instruction, which allows the cache controller to fetch the next 16-byte aligned set of instructions.
  • The PFMSECEN bit (CHECON[7]) controls the Prefetch module that generates an interrupt event on a specific count of single bit errors corrected by the Flash Error Correction Code (ECC).
  • The ADRWS bit (CHECON[8]) controls the number of system clock cycles required for address setup to PFM.
  • The CHEPERF bit (CHECON[12]) controls the gathering statistics of the CPU instruction cache.
  • The ICHECOH bit (CHECON[16]) controls the auto invalidate for the CPU instruction cache.
  • The DCHECOH bit (CHECON[17]) controls the auto invalidate for the CPU data cache.
  • The ACHECOH bit (CHECON[18]) controls the auto invalidate for the peripheral data cache.
  • The ICHEINV bit (CHECON[20]) controls the manual invalidate for the CPU instruction cache.
  • The DCHEINV bit (CHECON[21]) controls the manual invalidate for the CPU data cache.
  • The ACHEINV bit (CHECON[22]) controls the manual invalidate for the peripheral data cache.
  • The ICHEEN bit (CHECON[24]) controls the CPU instruction cache enable.
  • The DCHEEN bit (CHECON[25]) controls the CPU data cache enable.
  • The ACHEEN bit (CHECON[26]) controls the peripheral data cache enable.