17.2 Features

The Clock and Reset Unit has the following features:

  • Supports the Following as System Clock Sources:
    • 16 MHz Primary Crystal Oscillator (POSC)
    • 8 MHz Fast RC Oscillator (FRC)
    • 32 kHz Low Power RC Oscillator (LPRC)
    • 32.768 kHz Secondary Crystal Oscillator (SOSC)
    • 64 MHz System PLL (RFPLLPGM MHz)
  • Provides Control Registers for PLL
  • Provides Glitch-Free Clock Switching Between Various Clock Sources
  • Post Dividers on Processor Clock Generator to Slow Down System Clock for Power Save
  • A Fail Safe Clock Monitor that Detects Clock Failure and Provides Automatic Switching to the FRC
  • Provides Control Registers for the User Interface of Clocks and Resets
  • Provides Configuration Bits for Oscillator Selection and Calibration of On-Chip Oscillators
  • Provides Control Registers to Generate a Reference Clock Output
  • Provide Resets for the System
  • Provides NMI for the System
  • Multiple PB Clock (Peripheral Clock) Dividers
  • One System Clock, SYS_CLK, which Almost All Clocks Used Throughout the System are Derived from
  • Three Peripheral Clocks, Created by Independent Integer Dividers of the SYS_CLK:
    • PB1_CLK: PB-Bridge-D and PB-Bridge-A
    • PB2_CLK: PB-Bridge-B and PB-Bridge-C
    • PB3_CLK: DS/XDS Bus Clock
  • Six Reference Output Clocks (REFO1 – REFO6) with the Following Clock Sources:
    • System clock (SYS_CLK)
    • PB1 Bus Clock (PB1_CLK)
    • 16 MHz Primary Crystal Oscillator (POSC)
    • 8 MHz Fast RC Oscillator (FRC)
    • 32 kHz Low Power RC Oscillator (LPRC)
    • 32.768 kHz Secondary Crystal Oscillator (SOSC)
    • 64 MHz system PLL (RFPLL PGM MHz), SPLL_CLK1
    • REFI pin
  • Provides Clock Source for Backup Core for Sleep Operations