23.2 Enabling Peripherals

The PMD register bits control the operation of individual peripherals on the device. When a peripheral’s associated PMD bit is ‘0’, the peripheral is enabled and operates as programmed. However, when the associated PMD bit is ‘1’, the peripheral logic, memory map and SFR bits are removed from visibility and the peripheral is held in Reset. This disabled state provides for the lowest power state of the peripheral.

Before a peripheral may be configured or used, clear the corresponding PMD register bit to enable the peripheral.

There are some caveats to use PMD bits. The following must be observed:
  1. Disabling a peripheral while its ON bit is ‘0’ results in an undefined behavior of the external interface.
  2. For bus initiators, the software must verify that the module is not busy after setting the ON bit to ‘0’ before disabling it.
  3. Setting the PMD bit when there is a pending interrupt results in undefined behavior. Therefore, all interrupt flags must be cleared before setting the associated PMD bit.