40.5.3 Clocks

The TC bus clocks (CLK_TCx_APB) can be enabled and disabled in the Clock and Reset Unit (CRU).

The generic clocks (GCLK_TCx) are asynchronous to the user interface clock (CLK_TCx_APB). Due to this asynchronicity, accessing certain registers will require synchronization between the clock domains.

Note: Two instances of the TC can share a peripheral clock channel. In this case, they cannot be set to different clock frequencies. See Clock and Reset Unit (CRU) from Related Links.

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