27.6.2.1 Initialization

The EIC must be initialized in the following order:

  1. If required, configure the NMI by writing the Non-Maskable Interrupt Control register (NMICTRL).
  2. Enable GCLK_EIC or 32KHz_LPCLK when one of the following configurations is selected:
    • The NMI uses edge detection or filtering
    • One EXTINT uses filtering
    • One EXTINT uses synchronous edge detection
    • One EXTINT uses debouncing

    GCLK_EIC is used when a frequency higher than 32 KHz is required for filtering.

    32KHz_LPCLK is recommended when power consumption is the priority. For 32KHz_LPCLK, write a ‘1’ to the Clock Selection bit in the Control A register (CTRLA.CKSEL).

  3. Configure the EIC input sense and filtering by writing the Configuration register (CONFIG).
  4. Optionally, enable the Asynchronous mode.
  5. Optionally, enable the Debouncer mode.
  6. Enable the EIC by writing a ‘1’ to CTRLA.ENABLE.

The following bits are enable-protected, meaning that they can only be written when the EIC is disabled (CTRLA.ENABLE=0):

  • Clock Selection bit in Control A register (CTRLA.CKSEL)

The following registers are enable-protected:

  • Event Control register (EVCTRL)
  • Configuration register (CONFIG)
  • External Interrupt Asynchronous mode register (ASYNCH)

  • Debouncer Enable register (DEBOUNCEN)

  • Debounce Prescaler register (DPRESCALER)

Enable-protected bits in the CTRLA register can be written at the same time when setting CTRLA.ENABLE to ‘1’ but not at the same time as CTRLA.ENABLE is being cleared.

Enable protection is denoted by the Enable-Protected property in the register description.

See the NMICTRL, CTRLA, CONFIG, ASYNCH, DEBOUNCEN, DPRESCALER, EVCTRL registers in the EIC Register Summary from Related Links.