33.5.1 I/O Lines
To use the SERCOM’s I/O lines, the I/O pins must be configured using the System Configuration registers (See System Configuration and Register Locking (CFG) from Related Links) (SCOM_HSEN[1:0] of CFGCON1/DEVCFG1 register) for direct or PPS configuration. If SERCOM pins are selected through PPS, the PPS registers have to be configured. See I/O Ports and Peripheral Pin Select (PPS) from Related Links.
If SCOMx_HSEN = 1, SERCOM uses dedicated pins.
If SCOMx_HSEN = 0, SERCOM uses PPS path and I/O pins are multiplexed to pins groups defined in PPS section.
When the SERCOM is configured for SPI operation, the SERCOM controls the direction and value of the I/O pins according to the following table. If the receiver is disabled, the data input pin can be used for other purposes. In Host mode, the SPI Select line (SS) is hardware-controlled when the Host SPI Select Enable bit in the Control B register (CTRLB.MSSEN) is ‘1’.
| Pin | Host SPI | Client SPI |
|---|---|---|
| MOSI | Output | Input |
| MISO | Input | Output |
| SCK | Output | Input |
| SS | Output (CTRLB.MSSEN = 1) | Input |
The configuration of the Data In Pinout and the Data Out Pinout bit groups in the Control A register (CTRLA.DIPO and CTRLA.DOPO) define the physical position of the SPI signals in the Table 33-2.