4.1.3.1 Data Input Bit Frames

A data input bit frame can be used by the host to transmit either a logic ‘0’ or logic ‘1’ data bit to the AT21CS01/AT21CS11. The input bit frame is initiated when the host drives the SI/O line low. The length of time that the SI/O line is held low will dictate whether the host is transmitting a logic ‘0’ or a logic ‘1’ for that bit frame. For a logic ‘0’ input, the length of time that the SI/O line must be held low is defined as t_LOW0. Similarly, for a logic ‘1’ input, the length of time that the SI/O line must be held low is defined as t_LOW1.

The AT21CS01/AT21CS11 will sample the state of the SI/O line after the maximum t_LOW1 but prior to the minimum t_LOW0 after SI/O is driven below the V_IL threshold to determine if the data input is a logic ‘0’ or a logic ‘1’. If the host is still driving the line low at the sample time, the AT21CS01/AT21CS11 will decode that bit frame as a logic ‘0’ as SI/O will be at a voltage less than V_IL. If the host has already released the SI/O line, the AT21CS01/AT21CS11 will see a voltage level greater than or equal to V_IH because of the external pull-up resistor, and that bit frame will be decoded as a logic ‘1’. The timing requirements for these parameters can be found in AT21CS01/AT21CS11 AC Characteristics.

A logic ‘0’ condition has multiple uses in the I²C emulation sequences. It is used to signify a ‘0’ data bit, and it is also used for an Acknowledge (ACK) response. Additionally, a logic ‘1’ condition is used for a No Acknowledge (NACK) response in addition to the nominal ‘1‘ data bit.

Figure 4-2 and Figure 4-3 depict the logic ‘0’ and logic ‘1’ input bit frames.