22.6.2 Configuration

Table 22-4. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: CONFIG
Offset: 0x01
Reset: x initially determined from NVM User Row after reset
Property: PAC Write-Protection, Enable-Protected

Bit 76543210 
 WINDOW[3:0]PER[3:0] 
Access R/W/CFGR/W/CFGR/W/CFGR/W/CFGR/W/CFGR/W/CFGR/W/CFGR/W/CFG 
Reset xxxxxxxx 

Bits 7:4 – WINDOW[3:0] Window Mode Time-Out Period

In Window mode, these bits determine the watchdog closed window period as a number of cycles of the 1024 Hz CLK_WDT_OSC clock. These bits are loaded from User Configuration FUCFG0 at start-up.

ValueDescription
0x08 1kHz clock cycles
0x116 1kHz clock cycles
0x232 1kHz clock cycles
0x364 1kHz clock cycles
0x4128 1kHz clock cycles
0x5256 1kHz clock cycles
0x6512 1kHz clock cycles
0x71024 1kHz clock cycles
0x82048 1kHz clock cycles
0x94096 1kHz clock cycles
0xA8192 1kHz clock cycles
0xB 16384 1kHz clock cycles
0xC-0xFReserved

Bits 3:0 – PER[3:0]  Time-Out Period

These bits determine the watchdog time-out period as a number of 1024 Hz CLK_WDTOSC clock cycles. In Window mode operation, these bits define the open window period. These bits are loaded from User Configuration FUCFG0 at startup.

ValueDescription
0x08 1kHz clock cycles
0x116 1kHz clock cycles
0x232 1kHz clock cycles
0x364 1kHz clock cycles
0x4128 1kHz clock cycles
0x5256 1kHz clock cycles
0x6512 1kHz clock cycles
0x71024 1kHz clock cycles
0x82048 1kHz clock cycles
0x94096 1kHz clock cycles
0xA8192 1kHz clock cycles
0xB16384 1kHz clock cycles
0xC - 0xFReserved