22.6.7 Synchronization Busy
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | SYNCBUSY |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLEAR | ALWAYSON | RUNSTDBY | WEN | ENABLE | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 5 – CLEAR Clear Synchronization Busy
| Value | Description |
|---|---|
| 0 | Write synchronization of the CLEAR register is complete. |
| 1 | Write synchronization of the CLEAR register is ongoing. |
Bit 4 – ALWAYSON Always-On Synchronization Busy
| Value | Description |
|---|---|
| 0 | Write synchronization of the CTRLA.ALWAYSON bit is complete. |
| 1 | Write synchronization of the CTRLA.ALWAYSON bit is ongoing. |
Bit 3 – RUNSTDBY Run-In-Standby Synchronization Busy
| Value | Description |
|---|---|
| 0 | Write synchronization of the CTRLA.RUNSTDBY bit is complete. |
| 1 | Write synchronization of the CTRLA.RUNSTDBY bit is ongoing. |
Bit 2 – WEN Window Enable Synchronization Busy
| Value | Description |
|---|---|
| 0 | Write synchronization of the CTRLA.WEN bit is complete. |
| 1 | Write synchronization of the CTRLA.WEN bit is ongoing. |
Bit 1 – ENABLE Enable Synchronization Busy
| Value | Description |
|---|---|
| 0 | Write synchronization of the CTRLA.ENABLE bit is complete. |
| 1 | Write synchronization of the CTRLA.ENABLE bit is ongoing. |