27.12.4 Standby Configuration Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | STDBYCFG |
| Offset: | 0x08 |
| Reset: | 0x04 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LPRAM | RAMCFG | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 1 | 0 |
Bit 2 – LPRAM Low-Power RAM Enable
| Value | Description |
|---|---|
| 0x0 | System SRAM interface logic is powered on in Standby mode. |
| 0x1 | System SRAM interface logic is powered off, but SRAM contents are retained based on RAMCFG setting when in Standby mode. |
Note:
- These bits are don’t care if SLEEPCFG.SLEEPMODE ≠ 0x4, (i.e., not in Standby mode).
- When STDBYCFG.LPRAM = 0x1 and device is in Standby mode, (i.e., SLEEPCFG.SLEEPMODE = 0x4), system SRAMs interface logic is powered down, but SRAM contents are retained based on the PM.STDBYCFG.RAMCFG setting.
- This register is reset on entry into either Hibernate or Backup modes.
Bit 0 – RAMCFG RAM Configuration
| Value | Description |
|---|---|
| 0x0 | All system SRAM contents are retained. |
| 0x1 | No system SRAM contents are retained. |
Note:
- These bits are don’t care if SLEEPCFG.SLEEPMODE ≠ 0x4, (i.e., not in Standby mode).
- This register is reset on entry into either Hibernate or Backup modes.