27.12.2 Sleep Configuration
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | SLEEPCFG |
| Offset: | 0x01 |
| Reset: | 0x02 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SLEEPMODE[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 1 | 0 | ||||||
Bits 2:0 – SLEEPMODE[2:0] Sleep Mode
| Value | Name | Definition (1) |
|---|---|---|
| 0x0 – 0x1 | Reserved | - |
| 0x2 | IDLE | Idle sleep mode |
| 0x3 | Reserved | - |
| 0x4 | STANDBY | Standby sleep mode. |
| 0x5 | HIBERNATE | Hibernate sleep mode. |
| 0x6 | BACKUP | Backup sleep mode. |
| 0x7 | OFF | Off sleep mode. |
Note:
- Due to clock domain synchronization, a small latency occurs between the store instruction and actual writing of the SLEEPCFG.SLEEPMODE[2:0] bits. Software must ensure that the SLEEPCFG register reads the desired SLEEPMODE value before issuing the WFI instruction.
- Please refer to the Sleep Modes section for more details on sleep modes definition and behavior.
- This register is reset on entry into either HIBERNATE or BACKUP modes.