26.7.1 Interrupt Enable Clear
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTENCLR |
| Offset: | 0x0000 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ADDVREGRDY2 | ADDVREGRDY1 | ADDVREGRDY0 | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BORVDDUSB1 | BORVDDUSB0 | LVDRDY | LVDET | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 8, 9, 10 – ADDVREGRDYn Additional Regulator n Ready Interrupt Enable Clear , n = 0 for USB-PHY0, n = 1 for USB-PHY1, and n = 2 for PLL
Writing a zero to these bits has no effect.
Writing a one to a bit disables the corresponding ADDVREGRDYn interrupt.
Each bit will read as the current value of the ADDVREGRDYn interrupt enable.
Bits 5, 6 – BORVDDUSBn BORVDDUSBn Interrupt Enable Clear, n = 0,1
Writing a zero to these bits has no effect.
Writing a one to a bit disables the corresponding BORVDDUSBn interrupt.
Each bit will read as the current value of the BORVDDUSBn interrupt enable.
Bit 1 – LVDRDY Low Voltage Detector Ready Interrupt Enable Clear
Writing a zero to this bit has no effect.
Writing a one to this bit disables the LVDRDY interrupt.
This bit will read as the current value of the LVDRDY interrupt enable.
Bit 0 – LVDET Low Voltage Detector Interrupt Enable Clear
Writing a zero to this bit has no effect.
Writing a one to this bit disables the LVDET interrupt.
This bit will read as the current value of the LVDET interrupt enable.