16.13.10 Status C
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | STATUSC |
| Offset: | 0x0108 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| INDEX[4:0] | |||||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| STATE[4:0] | |||||||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 12:8 – INDEX[4:0] Shows MBIST bit Index
Bits 4:0 – STATE[4:0] Core State
0x0 = State Machine Ready (IDLE)
0x1 = CRC32 operation ongoing (CRC32)
0x2-0x3 = Reserved
0x4 = Memory Set (MSET)
0x5-0x7 = Reserved
0x8 = MBIST fill memory with zeroes (MBIST FILL)
0x9 = SET1 Phase: read 0'write'1'(MBIST SET1)'
0xA = SET2 Phase: read 1'write'0'(MBIST SET2)'
0xB = SET2B Phase: read 0'write'1'(MBIST SET2B)'
0xC = CLEAR1 Phase: read 1'write'0'(MBIST CLEAR1)'
0xD = CLEAR2 Phase: read 0'write'1'(MBIST CLEAR2)'
0xE = CLEAR2B Phase: read 1'write'0'(MBIST CLEAR2B)'
0xF = READ Phase: check memory is cleared (MBIST_READ)
0x10-0x1F = Reserved