38.7.33 Rx Buffer / FIFO Element Size
Configuration
This register is write-restricted and only writable if bit fields
CCCR.CCE bit (CCCR <1>) = 1 and CCCR.INIT bit (CCCR <0>) = 1.
Configures the number of data bytes belonging to an Rx Buffer / Rx FIFO
element. Data field sizes >8 bytes are intended for CAN FD operation only.
Table 38-50. Register Bit Attribute
LegendSymbol | Description | Symbol | Description | Symbol | Description |
---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | RXESC |
Offset: | 0xBC |
Reset: | 0x00000000 |
Property: | Write-restricted |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | RBDS[2:0] | |
Access | | | | | | R/W | R/W | R/W | |
Reset | | | | | | 0 | 0 | 0 | |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | F1DS[2:0] | | F0DS[2:0] | |
Access | | R/W | R/W | R/W | | R/W | R/W | R/W | |
Reset | | 0 | 0 | 0 | | 0 | 0 | 0 | |
Bits 10:8 – RBDS[2:0] Rx Buffer Data
Field Size
In case the data
field size of an accepted CAN frame exceeds the data field size configured for the
matching Rx Buffer, only the number of bytes as configured by RXESC are stored to
the Rx Buffer element. The rest of the frame’s data field is
ignored.Value | Name | Description |
---|
0x0 | DATA8 | 8 byte
data field. |
0x1 | DATA12 | 12 byte
data field. |
0x2 | DATA16 | 16 byte
data field. |
0x3 | DATA20 | 20 byte
data field. |
0x4 | DATA24 | 24 byte
data field. |
0x5 | DATA32 | 32 byte
data field. |
0x6 | DATA48 | 48 byte
data field. |
0x7 | DATA64 | 64 byte
data field. |
Bits 6:4 – F1DS[2:0] Rx FIFO 1 Data
Field Size
In case the data
field size of an accepted CAN frame exceeds the data field size configured for the
matching Rx FIFO 1, only the number of bytes as configured by RXESC are stored to
the Rx FIFO 1 element. The rest of the frame’s data field is
ignored.Value | Name | Description |
---|
0x0 | DATA8 | 8 byte
data field. |
0x1 | DATA12 | 12 byte
data field. |
0x2 | DATA16 | 16 byte
data field. |
0x3 | DATA20 | 20 byte
data field. |
0x4 | DATA24 | 24 byte
data field. |
0x5 | DATA32 | 32 byte
data field. |
0x6 | DATA48 | 48 byte
data field. |
0x7 | DATA64 | 64 byte
data field. |
Bits 2:0 – F0DS[2:0] Rx FIFO 0 Data
Field Size
In case the data
field size of an accepted CAN frame exceeds the data field size configured for the
matching Rx FIFO 0, only the number of bytes as configured by RXESC are stored to
the Rx FIFO 0 element. The rest of the frame’s data field is
ignored.Value | Name | Description |
---|
0x0 | DATA8 | 8 byte
data field. |
0x1 | DATA12 | 12 byte
data field. |
0x2 | DATA16 | 16 byte
data field. |
0x3 | DATA20 | 20 byte
data field. |
0x4 | DATA24 | 24 byte
data field. |
0x5 | DATA32 | 32 byte
data field. |
0x6 | DATA48 | 48 byte
data field. |
0x7 | DATA64 | 64 byte
data field. |