20.7.4 Peripheral Channel Control

PCHCTRLm controls the settings of Peripheral Channel number m (m=0..63).

Important: PCHCTRLm values, where m = 52 and m = 53, are Reserved.

Table 20-11. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	PCHCTRLm
Offset:	0x80 + m*0x04 [m=0..63]
Reset:	0x00000000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	WRTLOCK	CHEN			GEN[3:0]
Access	R/W	R/W			R/W	R/W	R/W	R/W
Reset	0	0			0	0	0	0

Bit 7 – WRTLOCK Write Lock

After this bit is set to '1', further writes to the PCHCTRLm register will be discarded. The control register of the corresponding Generator n (GENCTRLn), as assigned in PCHCTRLm.GEN, will also be locked. It can only be unlocked by a Power Reset.

Note that Generator 0 cannot be locked.

Value	Description
0	The Peripheral Channel register and the associated Generator register are not locked
1	The Peripheral Channel register and the associated Generator register are locked

Bit 6 – CHEN Channel Enable

This bit is used to enable and disable a Peripheral Channel.

Value	Description
0	The Peripheral Channel is disabled
1	The Peripheral Channel is enabled

Bits 3:0 – GEN[3:0] Generator Selection

This bit field selects the Generator to be used as the source of a peripheral clock, as shown in the table below:

Table 20-12. Generator Selection
Value	Description
0x0	Generic Clock Generator 0
0x1	Generic Clock Generator 1
0x2	Generic Clock Generator 2
0x3	Generic Clock Generator 3
0x4	Generic Clock Generator 4
0x5	Generic Clock Generator 5
0x6	Generic Clock Generator 6
0x7	Generic Clock Generator 7
0x8	Generic Clock Generator 8
0x9	Generic Clock Generator 9
0xA	Generic Clock Generator 10
0xB	Generic Clock Generator 11
0xC	Generic Clock Generator 12
0xD	Generic Clock Generator 13
0xE	Generic Clock Generator 14
0xF	Generic Clock Generator 15

Table 20-13. Reset Value after a User Reset or a Power Reset
Reset	PCHCTRLm.GEN	PCHCTRLm.CHEN	PCHCTRLm.WRTLOCK
Power Reset	0x0	0x0	0x0
User Reset	0x0	0x0	0x0

A power Reset will reset all the PCHCTRLm registers.

A user Reset will reset a PCHCTRL if WRTLOCK = 0, or else the content of that PCHCTRL remains unchanged.

The PCHCTRL register Reset values are shown in the table below, PCHCTRLm Mapping.

Table 20-14. PCHCTRL (Index) GCLK Mapping
Target Destination	GCLK Name	PCHCTRL(Index)
OSCCTRL	GCLK_OSCCTRL_DFLL48	0
	GCLK_OSCCTRL_PLL0	1
	GCLK_OSCCTRL_PLL1	2
FREQM	GCLK_FREQM_MSR	3
FREQM	GCLK_FREQM_REF	4
EIC	GCLK_EIC	5
EVSYS	GCLK_EVSYS_CH0	6
	GCLK_EVSYS_CH1	7
	GCLK_EVSYS_CH2	8
	GCLK_EVSYS_CH3	9
	GCLK_EVSYS_CH4	10
	GCLK_EVSYS_CH5	11
	GCLK_EVSYS_CH6	12
	GCLK_EVSYS_CH7	13
	GCLK_EVSYS_CH8	14
	GCLK_EVSYS_CH9	15
	GCLK_EVSYS_CH10	16
	GCLK_EVSYS_CH11	17
SERCOM0	GCLK_SERCOM0_SLOW	18
SERCOM1	GCLK_SERCOM1_SLOW
SERCOM4	GCLK_SERCOM4_SLOW
SERCOM2	GCLK_SERCOM2_SLOW	19
SERCOM3	GCLK_SERCOM3_SLOW
SERCOM5	GCLK_SERCOM5_SLOW
SERCOM6	GCLK_SERCOM6_SLOW
SERCOM7	GCLK_SERCOM7_SLOW	20
SERCOM8	GCLK_SERCOM8_SLOW
SERCOM9	GCLK_SERCOM9_SLOW
SERCOM0	GCLK_SERCOM0_CORE	21
SERCOM1	GCLK_SERCOM1_CORE	22
SERCOM2	GCLK_SERCOM2_CORE	23
SERCOM3	GCLK_SERCOM3_CORE	24
SERCOM4	GCLK_SERCOM4_CORE	25
SERCOM5	GCLK_SERCOM5_CORE	26
SERCOM6	GCLK_SERCOM6_CORE	27
SERCOM7	GCLK_SERCOM7_CORE	28
SERCOM8	GCLK_SERCOM8_CORE	29
SERCOM9	GCLK_SERCOM9_CORE	30
TCC0	GCLK_TCC0	31
TCC1	GCLK_TCC1	32
TCC2	GCLK_TCC2	33
TCC6	GCLK_TCC6	37
TCC7	GCLK_TCC7	38
TCC8	GCLK_TCC8	39
TCC9	GCLK_TCC9	40
ADC	GCLK_ADC	41
AC	GCLK_AC	42
PTC	GCLK_PTC	43
I2S0	GCLK_I2S0	44
I2S1	GCLK_I2S1	45
CAN0	GCLK_CAN0	46
CAN1	GCLK_CAN1	47
CAN2	GCLK_CAN2	48
CAN3	GCLK_CAN3	49
CAN4	GCLK_CAN4	50
CAN5	GCLK_CAN5	51
RSVD	---	52
RSVD	---	53
GMAC	GCLK_GMAC_TX	54
GMAC	GCLK_GMAC_TSU	55
SQI0	GCLK_SQI0	56
SQI1	GCLK_SQI1	57
SDHC0	GCLK_SDHC0_CORE	58
SDHC0	GCLK_SDHC0_SLOW	59
SDHC1	GCLK_SDHC1_CORE	60
SDHC1	GCLK_SDHC1_SLOW	61
MLB	GCLK_MLB	62
TRACE	GCLK_CM7_TRACE	63

Important: The GCLK_SERCOMn_SLOW setting must only be used for the I²C operating mode.

PIC32CZ CA80/CA90 Family

20.7.4 Peripheral Channel Control

Bit 7 – WRTLOCK Write Lock

Bit 6 – CHEN Channel Enable

Bits 3:0 – GEN[3:0] Generator Selection