29.6.2 External Pin Processing

Each external pin can be configured to generate an interrupt/event on edge detection (rising, falling or both edges) or level detection (high or low). The sense of external interrupt pins is configured by writing the Input Sense x bits in the External Interrupt Sense Configuration n register (CONFIGn.SENSEx). The corresponding interrupt flag (INTFLAG.EXTINT[x]) in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition is met.

When the interrupt flag has been cleared in edge-sensitive mode, INTFLAG.EXTINT[x] will only be set if a new interrupt condition is met.

In level-sensitive mode, when interrupt has been cleared, INTFLAG.EXTINT[x] will be set immediately if the EIC_EXTINTx pin still matches the interrupt condition.

Each external pin can be filtered by a majority vote filtering, clocked by GCLK EIC or CLK ULP32K. Filtering is enabled if bit Filter Enable x in the Configuration n register (CONFIG.FILTENx) is written to '1'. The majority vote filter samples the external pin three times with GCLK EIC or CLK ULP32K and outputs the value when two or more samples are equal.

Table 29-1. Majority Vote Filter
Samples [0, 1, 2]Filter Output
[0,0,0]0
[0,0,1]0
[0,1,0]0
[0,1,1]1
[1,0,0]0
[1,0,1]1
[1,1,0]1
[1,1,1]1

When an external interrupt is configured for level detection and when filtering is disabled, detection is done asynchronously. Level detection and asynchronous edge detection does not require GCLK EIC or CLK ULP32K, but interrupt and events can still be generated.

If filtering or synchronous edge detection or debouncing is enabled, the EIC automatically requests GCLK EIC or CLK ULP32K to operate. The selection between these two clocks is done by writing the Clock Selection bits in the Control A register (CTRLA.CKSEL). GCLK EIC must be enabled in the GCLK module. In these modes the external pin is sampled at the EIC clock rate, thus pulses with duration lower than two EIC clock periods may not be properly detected.

Figure 29-2. Interrupt Detection Latency by Modes (Rising Edge)

The detection latency depends on the detection mode.

Table 29-2. Detection Latency
Detection modeLatency (worst case)
Level without filterFive CLK EIC APB periods
Level with filterFour GCLK EIC/CLK ULP32K periods + five CLK EIC APB periods
Edge without filterFour GCLK EIC/CLK ULP32K periods + five CLK EIC APB periods
Edge with filterSix GCLK EIC/CLK ULP32K periods + five CLK EIC APB periods