41.5.2.1 Initialization
- Configure the clock source for CLK_TRNG_APB in the Main Clock Controller (MCLK) and enable the clock by writing a ‘1’ to the TRNG bit in the APB Mask register of the MCLK
- Enable the TRNG operation by writing a ‘1’ to CTRLA.ENABLE bit (CTRLA.ENABLE <1>)
- When the INTFLAG.DATARDY bit (INTFLAG <0>) is set, read the Output Data register (DATA<31:0>) to get the newly generated random number
Note:
- INTFLAG.DATARDY bit (INTFLAG <0>) is cleared automatically when the DATA register is read.
- It is necessary to wait 100ms after the TRNG is enabled before use to allow for target entropy to be achieved.