41.5.3 Interrupts
The TRNG module has the TRNG Data Ready (TRNG_READY) interrupt source, which indicates that a new random number is available in the DATA register and ready to be read.
The interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.DATARDY (INTFLAG <0>)) is set to ‘1’ when the interrupt condition occurs. The interrupt can be enabled by writing a '1' to the INTENSET.DATARDY bit (INTENSET <0>) in the Interrupt Enable Set register and disabled by writing a '1' to the INTENCLR.DATARDY bit (INTENCLR <0>) in the Interrupt Enable Clear (INTENCLR) register.
The interrupt request line is connected to the Nested Vector Interrupt Controller (NVIC). Using the TRNG interrupt requires the interrupt controller to be configured first. Refer to Nested Vector Interrupt Controller for details. This interrupt is a synchronous wake-up source. Refer to the Sleep Mode Controller for details.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, or the interrupt is disabled. See INTFLAG Status and Clear register for details on how to clear interrupt flags.
- Configure the NVIC by setting group priority, sub priority, and by enabling the TRNG IRQ (Vector No 210)
- Enable TRNG interrupt by setting the INTENSET.DATARDY bit (INTENSET<0>)
- Generated 32-bit random number is read from the Output data register (DATA<31:0>) in the TRNG Interrupt Service Routine (TRNG_ISR)
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