18.5.3 Clocks

The OSCCTRL gathers controls for all device oscillators and provides clock sources to the Generic Clock Controller (GCLK). The available clock sources are: XOSC, DFLL48M, PLLn_CLKOUT (n = 0,1) and FRACDIV.

The DFLL48M requires a reference clock (GCLK_DFLL48M_REF) from the GCLK. The control logic uses the oscillator output, which is asynchronous to the user interface clock (CLK_OSCCTRL_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. For additional information, refer to the Synchronization.

The PLLn requires a reference clock (GCLK_PLL_REF) from the GCLK when the PLL reference selector PLLCTRL.REFSEL is set to GCLK.

The FRACDIV control logic uses the fractional divider output, which is asynchronous to the user interface clock (CLK_OSCCTRL_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to Synchronization for further details.