18.6.8 OSCCTRL Synchronization

Due to the multiple clock domains, some registers in the DFLL48M must be synchronized when accessed. A register can require:

  • Synchronization when written
  • Synchronization when read
  • No synchronization When executing an operation that requires synchronization, the relevant synchronization bit in the Synchronization Busy register (DFLLSYNC) will be set immediately and cleared when synchronization is complete

The following registers need synchronization:

  • ENABLE bit in DFLLCTRLA register - write-synchronized
  • DFLLCTRLB register - read-synchronized
  • DFLLTUNE register - read- and write-synchronized
  • DFLLMUL register - write-synchronized
  • FRACDIV