27.6 Basic Operation

Initialization

After a power-on reset (POR), the PM is enabled, the device is in Active mode, and all the power domains are in active nominal power and voltage state.

Enabling, Disabling and Resetting

The PM is always enabled and cannot be disabled. It is reset to the default setting as defined in the register descriptions on a power up POR event. All of the registers with the exception of the PM.CTRLA are reset on entry into BACKUP or HIBERNATE modes.

Sleep Mode Controller

The sleep mode bits in the Sleep Configuration (SLEEPCFG.SLEEPMODE[2:0]) register select the MCU sleep mode. Sleep mode is subsequently entered by executing the Wait For Interrupt (WFI) instruction in the users code.

Important: Due to clock domain synchronization, a small latency occurs between the store instruction and actual writing of the SLEEPCFG.SLEEPMODE[2:0] bits. Software must ensure that the SLEEPCFG register reads the desired SLEEPMODE value before issuing the WFI instruction.
Table 27-8. Sleep Mode Entry and Wake-Up Sources
ModeMode EntryWake-Up Source
IDLESLEEPCFG.SLEEPMODE = IDLE (0x2)Asynchronous (1), Synchronous (2) (APB, AHB),
STANDBYSLEEPCFG.SLEEPMODE = STANDBY (0x4)Asynchronous (1), Synchronous (3)
HIBERNATESLEEPCFG.SLEEPMODE = HIBERNATE (0x5)Hibernate reset detected by the RSTC, Reset Controller
BACKUPSLEEPCFG.SLEEPMODE = BACKUP (0x6) (5)Backup reset detected by the RSTC, Reset Controller
OFFSLEEPCFG.SLEEPMODE = OFF (0x7)External reset
Note:
  1. Asynchronous interrupt generated on generic clock, external clock, or external event.
  2. Synchronous interrupt generated on synchronous (APB or AHB) clock.
  3. Synchronous interrupt only for peripherals configured to run in standby.
  4. The type of wake-up sources (synchronous or asynchronous) is given in each module interrupt section.
  5. Before entering backup sleep mode, it is recommended to poll the Backup Sleep Mode Enter Ready bit in the Interrupt Flag register (INTFLAG.SLEEPRDY) to make sure that the backup regulator is ready. If the WFI instruction is executed when this flag is not yet set the system will go in a “pseudo” backup mode where the PD_CORE_SW power domain is turned OFF, but the VREGRAM is still used. Then the system will go to backup sleep mode once the flag is set.

I/O Lines Retention in Hibernate or Backup Mode

When entering hibernate or backup sleep modes, the PORT peripheral is powered off, but the pin configuration is retained. When the device exits hibernate or backup sleep mode, the I/O line configuration can either be released or stretched, based on the I/O Retention bit in the Control A register (CTRLA.IORET).

  • If PM.CTRL.IORET = 0 when exiting hibernate or backup sleep modes, the I/O lines configuration is released and driven by the reset value of the PORT peripheral
  • If PM.CTRL.IORET = 1 when exiting hibernate or backup sleep modes, the configuration of the I/O lines is retained until the IORET bit is written to 0. It allows the I/O lines to be retained until the application has programmed the PORT peripheral.
Important: After setting PM.CTRL.IORET = 1, any subsequent attempt by the user to change or re-initialize a PORT value, even after a non-POR reset event, or exit from BACKUP or HIBERNATE by the user will not present themselves on the PORT’s until user clears PM.CTRL.IORET bit. The PM.CTRL.IORET bit is only cleared by silicon on a POR event which will also reset the PORT values to input, high impedance state.