42.3 Block Diagram

There are four ADC modules in the ADC and each controlled by common logic. Each ADC module has a dedicated Analog Input Multiplexer, which can select from seven up to 16 different analog inputs depending on the ADC module. Each ADC module has a Post Processing Block, consisting of a dedicated Digital Filter, and a dedicated Digital Comparator.

The ADC’s sample data is available in a single ADC Channel Ready Data Register (CHRDYDAT) and a 16-sample-deep FIFO (PFFDATA).

The ADC module provides five interrupts to the NVIC: one Global Interrupt and four ADC module-specific interrupts. Global interrupts are serviced by the CTLINTENCLR, CTLINTENSET, and CTLINTFLAG registers, while each ADCn module’s interrupts are serviced by INTENCLRn, INTENSETn, and INTFLAGn registers (where ADCn = 0,1,2,3).

The ADC runs on a peripheral clock provided by the Generic Clock (GCLK) module, known as the GCLK_ADC, and identified as ADC Control Clock, or CTL_CLK in this chapter. Each of the four ADC Modules has a clock derived from the ADC Control Clock, CORE_CLK[n], n=0,1,2,3. ADC Special Function Registers (SFRs) are identified as to which clock domain they belong: “APB_CLK” for the APB/Main Clock and “GCLK” for the clock derived from the GCLK, i.e. the ADC Control Clock (CTL_CLK).

The ADC Data Bus is 19 bits wide: { ChannelValid, CoreChannelID[5:0], ChannelData{11:0] }. The output results of each of the four ADC modules are stacked onto the bus in a 4:1 Time Division Multiplexing (TDM) scheme and the ChannelValid signal identifies whether the core’s time slot contains valid data. The input channel index is reported in the CoreChannelID bits. The captured signal is reported in the 12 bits of ChannelData.

The ADC Data Bus sends data to the ADC’s status and data registers as well as to the Digital Filter and Digital Comparator Post Processing Blocks. The bus also supports sending filtered results to the ADC’s data registers.