42.7 Register Summary

For descriptions and definitions of both Register and bitfield properties, refer to Register Properties.


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	CTRLA	31:24
		23:16
		15:8
		7:0	ONDEMAND	RUNSTDBY				ANAEN	ENABLE	SWRST
0x04	CTRLB	31:24
		23:16
		15:8	SWCNVEN				STRGEN	TRGSUSP	LSWTRG	GSWTRG
		7:0	SAMP	RQCNVRT	ADCORSEL[1:0]		ADCHSEL[3:0]
0x08	CTRLC	31:24		COREINTERLEAVED[2:0]
		23:16
		15:8	CNT[15:8]
		7:0	CNT[7:0]
0x0C ... 0x0F	Reserved
0x10	CTRLD	31:24		VREFSEL[2:0]			WKUPCLKCNT[3:0]
		23:16	ANLEN3	ANLEN2	ANLEN1	ANLEN0	CHNEN3	CHNEN2	CHNEN1	CHNEN0
		15:8			CTLCKDIV[5:0]
		7:0
0x14 ... 0x1F	Reserved
0x20	CONFIG0.CORCTRL	31:24		ADCDIV[6:0]
		23:16		SCNRTDS	STRGLVL		STRGSRC[3:0]
		15:8	EIRQOVR	EIS[2:0]			SELRES[1:0]		SAMC[9:8]
		7:0	SAMC[7:0]
0x24	CONFIG[0].CHNCFG1	31:24	LVL15	LVL14	LVL13	LVL12	LVL11	LVL10	LVL9	LVL8
		23:16	LVL7	LVL6	LVL5	LVL4	LVL3	LVL2	LVL1	LVL0
		15:8	CHNCMPE15	CHNCMPE14	CHNCMPE13	CHNCMPE12	CHNCMPE11	CHNCMPE10	CHNCMPE9	CHNCMPE8
		7:0	CHNCMPE7	CHNCMPE6	CHNCMPE5	CHNCMPE4	CHNCMPE3	CHNCMPE2	CHNCMPE1	CHNCMPE0
0x28	CONFIG[0].CHNCFG2	31:24	FRAC15	FRAC14	FRAC13	FRAC12	FRAC11	FRAC10	FRAC9	FRAC8
		23:16	FRAC7	FRAC6	FRAC5	FRAC4	FRAC3	FRAC2	FRAC1	FRAC0
		15:8	CSS15	CSS14	CSS13	CSS12	CSS11	CSS10	CSS9	CSS8
		7:0	CSS7	CSS6	CSS5	CSS4	CSS3	CSS2	CSS1	CSS0
0x2C	CONFIG[0].CHNCFG3	31:24	SIGN15	SIGN14	SIGN13	SIGN12	SIGN11	SIGN10	SIGN9	SIGN8
		23:16	SIGN7	SIGN6	SIGN5	SIGN4	SIGN3	SIGN2	SIGN1	SIGN0
		15:8
		7:0
0x30	CONFIG[0].CHNCFG4	31:24	TRGSRC7[3:0]				TRGSRC6[3:0]
		23:16	TRGSRC5[3:0]				TRGSRC4[3:0]
		15:8	TRGSRC3[3:0]				TRGSRC2[3:0]
		7:0	TRGSRC1[3:0]				TRGSRC0[3:0]
0x34	CONFIG[0].CHNCFG5	31:24	TRGSRC15[3:0]				TRGSRC14[3:0]
		23:16	TRGSRC13[3:0]				TRGSRC12[3:0]
		15:8	TRGSRC11[3:0]				TRGSRC10[3:0]
		7:0	TRGSRC9[3:0]				TRGSRC8[3:0]
0x38	CONFIG[0].CALCTRL	31:24	CALBITS[31:24]
		23:16	CALBITS[23:16]
		15:8	CALBITS[15:8]
		7:0	CALBITS[7:0]
0x3C	EVCTRL[0]	31:24
		23:16
		15:8
		7:0			CMPEO	RESRDYEO	STARTINV			STARTEI
0x40	CONFIG1.CORCTRL	31:24		ADCDIV[6:0]
		23:16		SCNRTDS	STRGLVL		STRGSRC[3:0]
		15:8	EIRQOVR	EIS[2:0]			SELRES[1:0]		SAMC[9:8]
		7:0	SAMC[7:0]
0x44	CONFIG[1].CHNCFG1	31:24
		23:16		LVL6	LVL5	LVL4	LVL3	LVL2	LVL1	LVL0
		15:8
		7:0		CHNCMPE6	CHNCMPE5	CHNCMPE4	CHNCMPE3	CHNCMPE2	CHNCMPE1	CHNCMPE0
0x48	CONFIG[1].CHNCFG2	31:24
		23:16		FRAC6	FRAC5	FRAC4	FRAC3	FRAC2	FRAC1	FRAC0
		15:8
		7:0		CSS6	CSS5	CSS4	CSS3	CSS2	CSS1	CSS0
0x4C	CONFIG[1].CHNCFG3	31:24
		23:16		SIGNn	SIGNn	SIGNn	SIGNn	SIGNn	SIGNn	SIGNn
		15:8
		7:0				DIFF4		DIFF2		DIFF0
0x50	CONFIG[1].CHNCFG4	31:24					TRGSRC6[3:0]
		23:16	TRGSRC5[3:0]				TRGSRC4[3:0]
		15:8	TRGSRC3[3:0]				TRGSRC2[3:0]
		7:0	TRGSRC1[3:0]				TRGSRC0[3:0]
0x54 ... 0x57	Reserved
0x58	CONFIG[1].CALCTRL	31:24	CALBITS[31:24]
		23:16	CALBITS[23:16]
		15:8	CALBITS[15:8]
		7:0	CALBITS[7:0]
0x5C	EVCTRL[1]	31:24
		23:16
		15:8
		7:0			CMPEO	RESRDYEO	STARTINV			STARTEI
0x60	CONFIG2.CORCTRL	31:24		ADCDIV[6:0]
		23:16		SCNRTDS	STRGLVL		STRGSRC[3:0]
		15:8	EIRQOVR	EIS[2:0]			SELRES[1:0]		SAMC[9:8]
		7:0	SAMC[7:0]
0x64	CONFIG[2].CHNCFG1	31:24
		23:16		LVL6	LVL5	LVL4	LVL3	LVL2	LVL1	LVL0
		15:8
		7:0		CHNCMPE6	CHNCMPE5	CHNCMPE4	CHNCMPE3	CHNCMPE2	CHNCMPE1	CHNCMPE0
0x68	CONFIG[2].CHNCFG2	31:24
		23:16		FRAC6	FRAC5	FRAC4	FRAC3	FRAC2	FRAC1	FRAC0
		15:8
		7:0		CSS6	CSS5	CSS4	CSS3	CSS2	CSS1	CSS0
0x6C	CONFIG[2].CHNCFG3	31:24
		23:16		SIGNn	SIGNn	SIGNn	SIGNn	SIGNn	SIGNn	SIGNn
		15:8
		7:0				DIFF4		DIFF2		DIFF0
0x70	CONFIG[2].CHNCFG4	31:24					TRGSRC6[3:0]
		23:16	TRGSRC5[3:0]				TRGSRC4[3:0]
		15:8	TRGSRC3[3:0]				TRGSRC2[3:0]
		7:0	TRGSRC1[3:0]				TRGSRC0[3:0]
0x74 ... 0x77	Reserved
0x78	CONFIG[2].CALCTRL	31:24	CALBITS[31:24]
		23:16	CALBITS[23:16]
		15:8	CALBITS[15:8]
		7:0	CALBITS[7:0]
0x7C	EVCTRL[2]	31:24
		23:16
		15:8
		7:0			CMPEO	RESRDYEO	STARTINV			STARTEI
0x80	CONFIG3.CORCTRL	31:24		ADCDIV[6:0]
		23:16		SCNRTDS	STRGLVL		STRGSRC[3:0]
		15:8	EIRQOVR	EIS[2:0]			SELRES[1:0]		SAMC[9:8]
		7:0	SAMC[7:0]
0x84	CONFIG[3].CHNCFG1	31:24
		23:16		LVL6	LVL5	LVL4	LVL3	LVL2	LVL1	LVL0
		15:8
		7:0		CHNCMPE6	CHNCMPE5	CHNCMPE4	CHNCMPE3	CHNCMPE2	CHNCMPE1	CHNCMPE0
0x88	CONFIG[3].CHNCFG2	31:24
		23:16		FRAC6	FRAC5	FRAC4	FRAC3	FRAC2	FRAC1	FRAC0
		15:8
		7:0		CSS6	CSS5	CSS4	CSS3	CSS2	CSS1	CSS0
0x8C	CONFIG[3].CHNCFG3	31:24
		23:16		SIGN6	SIGN5	SIGN4	SIGN3	SIGN2	SIGN1	SIGN0
		15:8
		7:0				DIFF4		DIFF2		DIFF0
0x90	CONFIG[3].CHNCFG4	31:24					TRGSRC6[3:0]
		23:16	TRGSRC5[3:0]				TRGSRC4[3:0]
		15:8	TRGSRC3[3:0]				TRGSRC2[3:0]
		7:0	TRGSRC1[3:0]				TRGSRC0[3:0]
0x94 ... 0x97	Reserved
0x98	CONFIG[3].CALCTRL	31:24	CALBITS[31:24]
		23:16	CALBITS[23:16]
		15:8	CALBITS[15:8]
		7:0	CALBITS[7:0]
0x9C	EVCTRL[3]	31:24
		23:16
		15:8
		7:0			CMPEO	RESRDYEO	STARTINV			STARTEI
0xA0 ... 0xAF	Reserved
0xB0	CMPCTRL[0]	31:24			IEHIHI	IEHILO	ADCMPHI[11:8]
		23:16	ADCMPHI[7:0]
		15:8	IEBTWN	IELOHI	IELOLO	CMPEN	ADCMPLO[11:8]
		7:0	ADCMPLO[7:0]
0xB4	CMPCTRL[1]	31:24			IEHIHI	IEHILO	ADCMPHI[11:8]
		23:16	ADCMPHI[7:0]
		15:8	IEBTWN	IELOHI	IELOLO	CMPEN	ADCMPLO[11:8]
		7:0	ADCMPLO[7:0]
0xB8	CMPCTRL[2]	31:24			IEHIHI	IEHILO	ADCMPHI[11:8]
		23:16	ADCMPHI[7:0]
		15:8	IEBTWN	IELOHI	IELOLO	CMPEN	ADCMPLO[11:8]
		7:0	ADCMPLO[7:0]
0xBC	CMPCTRL[3]	31:24			IEHIHI	IEHILO	ADCMPHI[11:8]
		23:16	ADCMPHI[7:0]
		15:8	IEBTWN	IELOHI	IELOLO	CMPEN	ADCMPLO[11:8]
		7:0	ADCMPLO[7:0]
0xC0	FLTCTRL[0]	31:24
		23:16
		15:8			FLTCHNID[3:0]					FLTEN
		7:0				DATA16EN	FMODE	OVRSAM[2:0]
0xC4	FLTCTRL[1]	31:24
		23:16
		15:8			FLTCHNID[3:0]					FLTEN
		7:0				DATA16EN	FMODE	OVRSAM[2:0]
0xC8	FLTCTRL[2]	31:24
		23:16
		15:8			FLTCHNID[3:0]					FLTEN
		7:0				DATA16EN	FMODE	OVRSAM[2:0]
0xCC	FLTCTRL[3]	31:24
		23:16
		15:8			FLTCHNID[3:0]					FLTEN
		7:0				DATA16EN	FMODE	OVRSAM[2:0]
0xD0	CORCHDATAID	31:24
		23:16
		15:8
		7:0			CORDYID[1:0]		CHRDYID[3:0]
0xD4	CHRDYDAT	31:24					FRACT	SIGN	DIFF	LVL
		23:16
		15:8	CHRDYDAT[15:8]
		7:0	CHRDYDAT[7:0]
0xD8	PFFDATA	31:24	PFFCNT[7:0]
		23:16	PFFFRACT	PFFSIGN	PFFCORID[1:0]		PFFCHNID[3:0]
		15:8	PFFDATA[15:8]
		7:0	PFFDATA[7:0]
0xDC ... 0xE3	Reserved
0xE4	PFFCTRL	31:24
		23:16								PFFRDYDMA
		15:8
		7:0	PFFCR3	PFFCR2	PFFCR1	PFFCR0			PFFEN
0xE8	SYNCBUSY	31:24
		23:16
		15:8
		7:0						CTRLB	ENABLE	SWRST
0xEC ... 0xFB	Reserved
0xFC	CTLINTENSET	31:24
		23:16
		15:8					PFFHFUL	PFFRDY	PFFOVF	PFFUNF
		7:0	VREFRDY	VREFUPD			CRRDY3	CRRDY2	CRRDY1	CRRDY0
0x0100	CTLINTENCLR	31:24
		23:16
		15:8					PFFHFUL	PFFRDY	PFFOVF	PFFUNF
		7:0	VREFRDY	VREFUPD			CRRDY3	CRRDY2	CRRDY1	CRRDY0
0x0104	CTLINTFLAG	31:24
		23:16
		15:8					PFFHFUL	PFFRDY	PFFOVF	PFFUNF
		7:0	VREFRDY	VREFUPD			CRRDY3	CRRDY2	CRRDY1	CRRDY0
0x0108 ... 0x011F	Reserved
0x0120	INTENCLR[0]	31:24	CHRDY[15:8]
		23:16	CHRDY[7:0]
		15:8					EOSRDY	CHNERRC	FLTRDY	CHRDYC
		7:0	SOVFL			CMPHIT
0x0124	INTENSET[0]	31:24	CHRDY[15:8]
		23:16	CHRDY[7:0]
		15:8					EOSRDY	CHNERRC	FLTRDY	CHRDYC
		7:0	SOVFL			CMPHIT
0x0128	INTFLAG[0]	31:24	CHRDY[15:8]
		23:16	CHRDY[7:0]
		15:8	CRDYID[3:0]				EOSRDY	CHNERRC	FLTRDY	CHRDYC
		7:0	SOVFL			CMPHIT	CMPINTID[3:0]
0x012C ... 0x012F	Reserved
0x0130	INTENCLR[1]	31:24	CHRDY[15:8]
		23:16	CHRDY[7:0]
		15:8					EOSRDY	CHNERRC	FLTRDY	CHRDYC
		7:0	SOVFL			CMPHIT
0x0134	INTENSET[1]	31:24	CHRDY[15:8]
		23:16	CHRDY[7:0]
		15:8					EOSRDY	CHNERRC	FLTRDY	CHRDYC
		7:0	SOVFL			CMPHIT
0x0138	INTFLAG[1]	31:24	CHRDY[15:8]
		23:16	CHRDY[7:0]
		15:8	CRDYID[3:0]				EOSRDY	CHNERRC	FLTRDY	CHRDYC
		7:0	SOVFL			CMPHIT	CMPINTID[3:0]
0x013C ... 0x013F	Reserved
0x0140	INTENCLR[2]	31:24	CHRDY[15:8]
		23:16	CHRDY[7:0]
		15:8					EOSRDY	CHNERRC	FLTRDY	CHRDYC
		7:0	SOVFL			CMPHIT
0x0144	INTENSET[2]	31:24	CHRDY[15:8]
		23:16	CHRDY[7:0]
		15:8					EOSRDY	CHNERRC	FLTRDY	CHRDYC
		7:0	SOVFL			CMPHIT
0x0148	INTFLAG[2]	31:24	CHRDY[15:8]
		23:16	CHRDY[7:0]
		15:8	CRDYID[3:0]				EOSRDY	CHNERRC	FLTRDY	CHRDYC
		7:0	SOVFL			CMPHIT	CMPINTID[3:0]
0x014C ... 0x014F	Reserved
0x0150	INTENCLR[3]	31:24	CHRDY[15:8]
		23:16	CHRDY[7:0]
		15:8					EOSRDY	CHNERRC	FLTRDY	CHRDYC
		7:0	SOVFL			CMPHIT
0x0154	INTENSET[3]	31:24	CHRDY[15:8]
		23:16	CHRDY[7:0]
		15:8					EOSRDY	CHNERRC	FLTRDY	CHRDYC
		7:0	SOVFL			CMPHIT
0x0158	INTFLAG[3]	31:24	CHRDY[15:8]
		23:16	CHRDY[7:0]
		15:8	CRDYID[3:0]				EOSRDY	CHNERRC	FLTRDY	CHRDYC
		7:0	SOVFL			CMPHIT	CMPINTID[3:0]

PIC32CZ CA80/CA90 Family

42.7 Register Summary