20.6.3.1 Enabling a Peripheral Clock

Before a Peripheral Clock is enabled, one of the Generators must be enabled (GENCTRLn.GENEN) and selected as source for the Peripheral Channel by setting the Generator Selection bits in the Peripheral Channel Control register (PCHCTRL.GEN). Any available Generator can be selected as clock source for each Peripheral Channel.

When a Generator has been selected, the peripheral clock is enabled by setting the Channel Enable bit in the Peripheral Channel Control register, PCHCTRLm.CHEN = 1. The PCHCTRLm.CHEN bit must be synchronized to the generic clock domain. PCHCTRLm.CHEN will continue to read as its previous state until the synchronization is complete.

Table 20-2. PCHCTRL (Index) GCLK Mapping
Target DestinationGCLK NamePCHCTRL(Index)
OSCCTRLGCLK_OSCCTRL_DFLL480
GCLK_OSCCTRL_PLL01
GCLK_OSCCTRL_PLL12
FREQMGCLK_FREQM_MSR3
GCLK_FREQM_REF4
EICGCLK_EIC5
EVSYSGCLK_EVSYS_CH06
GCLK_EVSYS_CH17
GCLK_EVSYS_CH28
GCLK_EVSYS_CH39
GCLK_EVSYS_CH410
GCLK_EVSYS_CH511
GCLK_EVSYS_CH612
GCLK_EVSYS_CH713
GCLK_EVSYS_CH814
GCLK_EVSYS_CH915
GCLK_EVSYS_CH1016
GCLK_EVSYS_CH1117
SERCOM0GCLK_SERCOM0_SLOW18
SERCOM1GCLK_SERCOM1_SLOW
SERCOM4GCLK_SERCOM4_SLOW
SERCOM2GCLK_SERCOM2_SLOW19
SERCOM3GCLK_SERCOM3_SLOW
SERCOM5GCLK_SERCOM5_SLOW
SERCOM6GCLK_SERCOM6_SLOW
SERCOM7GCLK_SERCOM7_SLOW20
SERCOM8GCLK_SERCOM8_SLOW
SERCOM9GCLK_SERCOM9_SLOW
SERCOM0GCLK_SERCOM0_CORE21
SERCOM1GCLK_SERCOM1_CORE22
SERCOM2GCLK_SERCOM2_CORE23
SERCOM3GCLK_SERCOM3_CORE24
SERCOM4GCLK_SERCOM4_CORE25
SERCOM5GCLK_SERCOM5_CORE26
SERCOM6GCLK_SERCOM6_CORE27
SERCOM7GCLK_SERCOM7_CORE28
SERCOM8GCLK_SERCOM8_CORE29
SERCOM9GCLK_SERCOM9_CORE30
TCC0GCLK_TCC031
TCC1GCLK_TCC132
TCC2GCLK_TCC233
TCC6GCLK_TCC637
TCC7GCLK_TCC738
TCC8GCLK_TCC839
TCC9GCLK_TCC940
ADCGCLK_ADC41
ACGCLK_AC42
PTCGCLK_PTC43
I2S0GCLK_I2S044
I2S1GCLK_I2S145
CAN0GCLK_CAN046
CAN1GCLK_CAN147
CAN2GCLK_CAN248
CAN3GCLK_CAN349
CAN4GCLK_CAN450
CAN5GCLK_CAN551
Reserved---52
Reserved---53
GMACGCLK_GMAC_TX54
GCLK_GMAC_TSU55
SQI0GCLK_SQI056
SQI1GCLK_SQI157
SDHC0GCLK_SDHC0_CORE58
GCLK_SDHC0_SLOW59
SDHC1GCLK_SDHC1_CORE60
GCLK_SDHC1_SLOW61
MLBGCLK_MLB62
TRACEGCLK_CM7_TRACE63