25.2 Features

  • 16 DMA channels
  • Linked-List gather & scatter programing model
  • Advanced split transaction AXI bus interface with bursting
  • Memory to Memory transfer capability
  • Memory to Peripheral transfers capability
  • Peripheral to Memory transfers capability
  • Peripheral to Peripheral transfer capability
  • Several different block transfer modes affecting the bus transfer protocol and speed with the following characteristics
    • Transfer sizes of up to 64KB
    • Byte Transfer Mode without burst
    • Half word Transfer Mode without burst
    • Auto Transfer Mode, where the DMA adjusts Transfer Modes to optimize transferred data
    • Fixed or Incrementing address modes
    • 32-bit Source and destination addresses
    • 64 bit Data path Support
  • Assignable channel priority level:
    • User assignable channel priorities
    • Fixed natural order priority arbitration
    • Priority levels may be shared.
    • QOS Support per priority group
    • Priority increase on event system trigger
  • Channel Start/Abort Triggers:
    • Software start trigger
    • Event system start trigger
    • Conditional start trigger
    • Event system abort trigger
    • Peripheral DMA request trigger
    • Enhanced pattern (data) match transfer termination
    • Bus fault abort
  • Multiple DMA channel status interrupts:
    • Transfer complete
    • Transfer started
    • Transfer midpoint reached
    • Transfer aborted
  • Single Clock Cycle CRC / Checksum Engine:
    • Provides independent CRC functions to each channel simultaneously (in parallel when activated)
    • Supports preprogrammed CRC-16 (IBM/ANSI), CRC-16 CCITT, CRC-32
    • Provides two user programmable polynomial registers for 32-bit or 16-bit CRCs. These registers are shared amongst the channels.
  • Event system output trigger per channel
  • APB connectivity for the SFRs