43.6.5 Internal DAC Operation
Each Analog Comparator pair, includes two DACs, each connected to its respective ACx.
The DACx is enabled when the analog comparator is enabled (COMPCTRLn = 1), and the DAC is used as positive or negative input for the respective comparator (MUXNEG = INTDAC or MUXPOS = INTDAC).
The DAC is disabled when the analog comparator is disabled (COMPCTRLn.ENABLE = 0).
The DAC configuration registers are cleared when the analog comparator is reset (CTRLA.SWRST = 1).
The DAC generates a reference voltage that is a fraction of the device’s supply voltage, with 128 levels. One independent DAC channel is dedicated for each comparator. The voltage of each channel is selected by the Value x bit field in the DACCTRL registers (DACCTRL.VALUEx).
The DAC can be enabled in continuous operating mode (DACCTRL.SHENx = 0), or in sample mode (DACCTRL.SHENx = 1). When set in continuous mode, no clocks are required for operation. In sampling mode, each DAC controller includes a dedicated counter, generating the sampling clock. The counter operation is started when the analog comparator is ready (STATUSB.READYx = 1), and stopped when the analog comparator is disabled. As a consequence, in single shot mode, the DAC is enabled in continuous mode when the AC is enabled (COMPCTRLn.ENABLE = 1), and switches to the sample and hold operation when the comparator is ready.
Note: the DAC S/H operating mode and AC single-shot mode are two independent operations, and not linked together. Both S/H and continuous DAC operating modes can be selected when the AC is used either continuous or single-shot mode. The operating modes must be selected by the application, depending on power consumption and/or response time requirements.
The counter counts up and restarted when software PERIOD programmable value (CTRLC.PER) is reached. The counter operation is stopped and the internal counter is cleared when the sampling and hold operation is not required. When the AC output toggles, the counter is restarted.
The sampling clock is set when the counter operation starts, and cleared when the counter reaches the WIDTH software programmable value (CTRLC.WIDTH).
