43.7 Register Summary

For descriptions and definitions of both Register and bitfield properties, refer to Register Properties.

OffsetNameBit Pos.76543210
0x00CTRLA31:24        
23:16        
15:8        
7:0      ENABLESWRST
0x02EVCTRL31:24      INVEI1INVEI0
23:16      COMPEI1COMPEI0
15:8       WINEO0
7:0      COMPEO1COMPEO0
0x04CTRLB31:24        
23:16        
15:8        
7:0      START1START0
0x08CTRLC31:24     PRESCALER[2:0]
23:16  PER[9:4]
15:8PER[3:0]  WIDTH[9:8]
7:0WIDTH[7:0]

0x0C

...

0x0F

Reserved         
0x10INTENCLR31:24        
23:16        
15:8       WIN0
7:0      COMP1COMP0
0x14INTENSET31:24        
23:16        
15:8       WIN0
7:0      COMPnCOMPn
0x18INTFLAG31:24        
23:16        
15:8       WIN0
7:0      COMP1COMP0
0x1CSTATUSA31:24        
23:16    WSTATE1[1:0]WSTATE0[1:0]
15:8        
7:0      STATE1STATE0
0x20STATUSB31:24        
23:16        
15:8        
7:0      READY1READY0
0x24DBGCTRL31:24        
23:16        
15:8        
7:0       DBGRUN
0x28SYNCBUSY31:24        
23:16        
15:8     WINCTRL0  
7:0    COMPCTRL1COMPCTRL0ENABLESWRST

0x2C

...

0x2F

Reserved         
0x30COMPCTRL031:24SUT[5:0]OUT[1:0]
23:16FLEN[2:0]HYST[1:0] SPEEDSWAP
15:8 MUXPOS[2:0] MUXNEG[2:0]
7:0 RUNSTDBYINTSEL[1:0]SINGLE ENABLE 

0x34

...

0x37

Reserved         
0x38DACCTRL031:24SHEN1       
23:16 VALUE1[6:0]
15:8SHEN0       
7:0 VALUE0[6:0]
0x3CWINCTRL31:24        
23:16        
15:8        
7:0     WINTSEL[1:0]WEN
0x40COMPCTRL131:24SUT[5:0]OUT[1:0]
23:16FLEN[2:0]HYST[1:0] SPEEDSWAP
15:8 MUXPOS[2:0] MUXNEG[2:0]
7:0 RUNSTDBYINTSEL[1:0]SINGLE ENABLE 

0x44

...

0x47

Reserved         
0x48DACCTRL131:24SHEN1       
23:16 VALUE1[6:0]
15:8SHEN0       
7:0 VALUE0[6:0]