44.5.2 Clocks

The TCC bus clocks (CLK_TCCx_APB) where x is 0,1,2...9 is enabled by default, and can be enabled or disabled in the Main Clock (MCLK).

A generic clock (GCLK_TCCx) is required to clock the TCC. This clock must be configured and enabled in the Generic Clock Controller (GCLK) before using the TCC.

The generic clocks (GCLK_TCCx) are asynchronous to the bus clock (CLK_TCCx_APB). Due to this asynchronicity, writing certain registers will require synchronization between the clock domains. Refer to Synchronization for further details.