44.6.2.1 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read.

The following bits are synchronized when written:

  • Software Reset and Enable bits in Control A register (CTRLA.SWRST and CTRLA.ENABLE)

The following registers are synchronized when written:

  • Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
  • Status register (STATUS)
  • Pattern and Pattern Buffer registers (PATT and PATTBUF)
  • Waveform register (WAVE)
  • Count Value register (COUNT)
  • Period Value and Period Buffer Value registers (PER and PERBUF)
  • Compare/Capture Channel y and Compare/Capture Channel y Buffer Value registers (CCy and CCBUFy)

The following registers are synchronized when read:

  • Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
  • Count Value register (COUNT): synchronization is done on demand through READSYNC command (CTRLBSET.CMD)
  • Pattern and Pattern Buffer registers (PATT and PATTBUF)
  • Waveform register (WAVE)
  • Period Value and Period Buffer Value registers (PER and PERBUF)
  • Compare/Capture Channel y and Compare/Capture Channel y Buffer Value registers (CCy and CCBUFy)

Required write synchronization is denoted by the “Write-Synchronized” property in the register description.

Required read synchronization is denoted by the “Read-Synchronized” property in the register description.

Reference:

  • Register Synchronization