20.6.2.3 Generic Clock Generator

Each Generator (GCLK_GEN) can be set to run from one of 14 different clock sources, GENCTRLn.SRC, except GCLK_GEN[1], which can be set to run from one of 13 sources, GCLK_GEN1 is invalid for GCLK_GEN1. GCLK_GEN[1] is the only Generator that can be selected as source to others Generators.

With respect to the GPIO[x] clock selection, GENCTRLx.SRC=0x01, each generator GCLK_GEN[x] can be connected to only one specific pin GCLK_IO[x] in a one-to-one GCLK_GENx to GCLK_IOx relationship. A pin GCLK_IO[x] can be set either to act as source to GCLK_GEN[x] or to output the clock signal generated by GCLK_GEN[x].

The selected source can be divided. Each Generator can be enabled or disabled independently.

Each GCLK_GEN clock signal can then be used as clock source for Peripheral Channels. Each Generator output is allocated to one or several Peripherals.

GCLK_GEN[0] is used as GCLK_MAIN for the synchronous clock controller inside the Main Clock Controller. Refer to the Main Clock Controller description for details on the synchronous clock generation.