17.7 Clocks after Reset

On any Reset the synchronous clocks start to their initial state:

  • DFLL48M is enabled and configured to run at 48MHz Open Loop
  • Generic Clock Generator 0 uses DFLL48M by default as a source and generates GCLK_MAIN and CLK_MAIN
  • CPU and BUS clocks are undivided and enabled

On a Power-on Reset, the 32KHz clock sources are reset and the GCLK module starts to its initial state:

  • All Generic Clock Generators are disabled except Generator 0
  • All Peripheral Channels in GCLK are disabled

On a User Reset the GCLK module starts to its initial state, except for:

  • Generic Clocks that are write-locked, i.e., the according WRTLOCK is set to 1 prior to Reset