17.1 Clock Distribution

The following are PIC32CZ CA clock system features:

• Clock sources, that is oscillators controlled by OSCCTRL and OSC32KCTRL
  • A clock source provides a time base that is used by other components, such as Generic Clock Generators. Example clock sources are the internal 48 MHz DFLL48M, Ultra low-power 32 kHz RC oscillator, OSCULP32K, PLL[0,1] and external oscillators XOSC and XOSC32K.

• Generic Clock Controller (GCLK), which generate, controls and distributes asynchronous clocks consisting of these:
  • Generic Clock Generators: These have programmable prescalers that can use any of the system clock sources. The Generic Clock Generator 0 generates the clock signal GCLK_MAIN, which is used by the CPU and Data Ram Tightly Coupled Memory, which in turn generates synchronous clocks.
  • Generic Clocks: These are clock signals generated by Generic Clock Generators. They are the Peripheral Channels and serve as clocks for the peripherals of the system. Multiple instances of a peripheral will typically have a separate Generic Clock.

• Main Clock Controller (MCLK)
  • The MCLK generates and controls the synchronous clocks for the system. This includes the CPU, bus clocks (Advanced High-performance Bus (AHB), Advanced Peripheral Bus (APB), and Advanced eXtensible Interface (AXI)), and the Special Function Register interfaces of the peripherals. It contains clock masks that can turn on/off the user interface of a peripheral as well as prescalers for the CPU and bus clocks.

The following figure illustrates an example, where SERCOM0 is clocked by the DFLL48M (RC 48 MHz) in Open-Loop mode. The DFLL48M is enabled, the Generic Clock Generator n uses the DFLL48M as its clock source and feeds into Peripheral Channel 21. The Generic Clock, also called GCLK_SERCOM0_CORE, is connected to SERCOM0 that supplies the functional logic clocks. The SERCOM0 interface, clocked by CLK_SERCOM0_APB, has been unmasked in the MCLK APB SERCOM0 mask register, MCLK.CLKMSK0.MSK31.