11.4.3 OSCCON3
Note:
- If CSWHOLD =
0, the user may not see this bit set (NOSCR =1). When the oscillator becomes ready, there may be a delay of one instruction cycle before NOSCR is set. The clock switch occurs in the next instruction cycle and NOSCR is cleared.
| Name: | OSCCON3 |
| Offset: | 0x028F |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CSWHOLD | ORDY | NOSCR | |||||||
| Access | R/W/HC | R | R | ||||||
| Reset | 0 | 0 | 0 |
Bit 7 – CSWHOLD Clock Switch Hold Control
| Value | Description |
|---|---|
| 1 | Clock switch (and interrupt) will hold when the oscillator selected by NOSC is ready |
| 0 | Clock switch will proceed when the oscillator selected by NOSC is ready |
Bit 4 – ORDY Oscillator Ready (read-only)
| Value | Description |
|---|---|
| 1 | OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC |
| 0 | A clock switch is in progress |
Bit 3 – NOSCR New Oscillator is Ready (read-only)(1)
| Value | Description |
|---|---|
| 1 | A clock switch is in progress and the oscillator selected by NOSC indicates a ‘ready’ condition |
| 0 | A clock switch is not in progress, or the NOSC-selected oscillator is not ready |