18.7.5 Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Table 18-9. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
R Readable bit HC Cleared by Hardware(Grey cell)Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit——
Name: INTENSET
Offset: 0x10
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
       ERRORREADY 
Access R/WR/W 
Reset 00 

Bit 1 – ERROR Error Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit sets the ERROR interrupt enable.

This bit will read as the current value of the ERROR interrupt enable.

Bit 0 – READY NVM Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit sets the READY interrupt enable.

This bit will read as the current value of the READY interrupt enable.