29.7.7 Status
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | STATUS |
| Offset: | 0x07 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SYNCBUSY | |||||||||
| Access | R | ||||||||
| Reset | 0 |
Bit 7 – SYNCBUSY Synchronization Busy Status
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.