12.7.1 Control
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRL |
| Offset: | 0x0 |
| Reset: | 0x00 |
| Property: | Write-Protected, Write-Synchronized |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWRST | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – SWRST Software Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the GCLK to their initial state after a Power Reset, except for generic clocks and associated generators that have their WRTLOCK bit in CLKCTRL read as one.
Refer to GENCTRL.ID for details on GENCTRL Reset.
Refer to GENDIV.ID for details on GENDIV Reset.
Refer to CLKCTRL.ID for details on CLKCTRL Reset.
Due to synchronization, there is a delay from writing CTRL.SWRST until the Reset is complete. CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the Reset is complete.
| Value | Description |
|---|---|
| 0 | There is no Reset operation ongoing |
| 1 | There is a Reset operation ongoing |