7.2 Physical Memory Map
The high-speed bus is implemented as a Bus Matrix. All high-speed bus addresses are fixed, and they are never remapped in any way, even during boot. The 32-bit physical address space is mapped as given in the below table.
Memory | Start Address | Size (Kbytes) | ||||
---|---|---|---|---|---|---|
PIC32CM3204 | PIC32CM1602 | |||||
Internal Flash | 0x00000000 | 32 | 16 | |||
Internal SRAM | 0x20000000 | 4 | 2 | |||
Peripheral Bridge A | 0x40000000 | 64 | 64 | |||
Peripheral Bridge B | 0x41000000 | 64 | 64 | |||
Peripheral Bridge C | 0x42000000 | 64 | 64 |
Device | Flash Size | Number of Pages | Page Size | Row Size |
---|---|---|---|---|
PIC32CM3204 | 32 Kbytes | 512 | 64 bytes | 4 pages = 256 bytes |
PIC32CM1602 | 16 Kbytes | 256 | 64 bytes | 4 pages = 256 bytes |
Note: The number of pages (NVMP) and page size (PSZ) can be read from the NVM Pages and
Page Size bits in the NVM Parameter register in the NVMCTRL (PARAM.NVMP and
PARAM.PSZ, respectively). Refer to NVM Parameter (PARAM) register for details.