7.2 Physical Memory Map

The high-speed bus is implemented as a Bus Matrix. All high-speed bus addresses are fixed, and they are never remapped in any way, even during boot. The 32-bit physical address space is mapped as given in the below table.

Table 7-1. Physical Memory Map
MemoryStart AddressSize (Kbytes)
PIC32CM3204PIC32CM1602
Internal Flash0x000000003216
Internal SRAM0x2000000042
Peripheral Bridge A0x400000006464
Peripheral Bridge B0x410000006464
Peripheral Bridge C0x420000006464
Table 7-2. Flash Memory Parameters
DeviceFlash SizeNumber of PagesPage SizeRow Size
PIC32CM320432 Kbytes51264 bytes4 pages = 256 bytes
PIC32CM160216 Kbytes25664 bytes4 pages = 256 bytes
Note: The number of pages (NVMP) and page size (PSZ) can be read from the NVM Pages and Page Size bits in the NVM Parameter register in the NVMCTRL (PARAM.NVMP and PARAM.PSZ, respectively). Refer to NVM Parameter (PARAM) register for details.