11.3.1.7 Software Reset Write Synchronization

Writing a '1' to the Software Reset bit in CTRL (CTRL.SWRST) will also trigger write synchronization and set STATUS.SYNCBUSY. When writing a '1' to the CTRL.SWRST bit it will immediately read as '1'. CTRL.SWRST and STATUS.SYNCBUSY will be cleared by hardware when the peripheral has been reset. Writing a zero to the CTRL.SWRST bit has no effect. The Synchronization Ready interrupt (if available) cannot be used for Software Reset write synchronization.

When the software Reset is in progress (STATUS.SYNCBUSY and CTRL.SWRST are '1'), attempt to do any of the following will cause the peripheral bus to stall until the Software Reset synchronization and the Reset is complete:

• Writing a Peripheral Core register
• Writing an APB register
• Reading a Read-synchronized register

APB registers can be read while the software Reset is being write-synchronized without causing the peripheral bus to stall.