1.2 External Interrupt Sensing

External interrupts can be sensed and registered either synchronously or asynchronously. Synchronous sensing requires I/O clock whereas asynchronous sensing does not requires I/O clock. This implies that the interrupts that are detected asynchronously can be used for waking the device from sleep modes other than idle mode because the I/O clock is halted in all sleep modes except idle mode.

The sense configuration for external interrupts and pin change interrupts for Atmel ATmega2560 is given in Table 1-2. For device specific sense configuration, refer to the respective datasheet.

Table 1-2. **External Interrupts Sense Configuration**
Program address	Interrupt source	Sensing
$0002	INT0	Asynchronous (Edges and level)
$0004	INT1	Asynchronous (Edges and level)
$0006	INT2	Asynchronous (Edges and level)
$0008	INT3	Asynchronous (Edges and level)
$000A	INT4	Synchronous (Edges and level)
$000C	INT5	Synchronous (Edges and level)
$000E	INT6	Synchronous (Edges and level)
$0010	INT7	Synchronous (Edges and level)
$0012	PCINT0	Asynchronous
$0014	PCINT1	Asynchronous
$0016	PCINT2	Asynchronous

From Table 1-2 all the pin change interrupts are detected asynchronously. Other interrupts (INT7:0) can be triggered by sensing the rising or falling edges or low level on the corresponding interrupt pins. The type of sensing (edge or level) for each of the INTn (n = 0 to 7 for Atmel ATmega2560) interrupts is software configurable using two Interrupt Sense Control (ISC) bits per interrupt. This is provided in the following table.

Table 1-3. **External Interrupts Individual Sense Configuration**
ISCn1	ISCn0	Description
0	0	The low level of INTn generates an interrupt request
0	1	Any edge of INTn generates an interrupt request
1	0	The falling edge of INTn generates an interrupt request
1	1	The rising edge of INTn generates an interrupt request

Note: PCINT23:0 does not have sense configuration options. This means that the interrupt will be generated whenever there is a logic change in the pin, that is, from high to low transition and low to high transition.