2.3 Layout Checklist
(Ask a Question)The following table provides the layout checklist.
| Guideline | Yes/No |
|---|---|
| Power | |
| Are the 0402 or lesser size capacitors used for all decapacitors? | |
| Is the required copper shape provided to core voltage? | |
| Are the required copper shape and sufficient vias provided to voltages? | |
| Are VREF planes for the DDRx reference supply isolated from the noisy planes? | |
| Are sufficient number of decoupling capacitors used for the DDRx core and VTT supply? | |
| Is one 0.1 µF capacitor for two VTT termination resistors used for DDRx? | |
| Is the VTT plane width sufficient? | |
| DDR Memories | |
| Are the length-match recommended by the vendor followed for DDR memories? | |
| XCVR | |
| Are the length-match recommendations for XCVR followed? | |
| Are DC blocking capacitors required for PCIe interface? | |
| Is tight-controlled impedance maintained along the XCVR traces? | |
| Are differential vias well designed to match XCVR trace impedance? | |
| Are DC blocking capacitor pads designed to match XCVR trace impedance? | |
| Dielectric Material | |
| Is proper PCB material selected for critical layers? |