2.2 Design Checklist

The following table lists the various checks that design engineers must take care while designing the system.

Table 2-1. Design Checklist
GuidelineYes/NoRemarks
Prerequisites
See PolarFire FPGA Datasheet

See UG0722: PolarFire FPGA Packaging and Pin Descriptions User Guide

See the board-level schematics of PolarFire Evaluation Kit.
Device Selection
Check for available device variants for PolarFire FPGA.

Select a device based on I/O pin count, transceivers, package, phase-locked loops (PLLs), and speed grade.

Check device errata in PolarFire Documentation.
Design Checklist
Power Analysis

Download the PolarFire Power Estimator and check for the power budget.

Power Supply Checklist

See Power Supplies for used power rails, and Figure 1-3 and Figure 1-4 for unused rails.

Decoupling Capacitors

Follow PolarFire Decoupling Capacitors. Perform PI Analysis for any deviation from the recommended capacitors.

Clocks
For more information about dynamic phase shift ports, see the “Dynamic Phase Shift Ports” table in PolarFire Family Clocking Resources User Guide .

The XCVR reference clock ranges from 20 MHz to 400 MHz.

The global clock network is driven by any of the following:
  • Preferred clock inputs (CLKIN_z_w)
  • On-chip oscillators
  • CCC (PLL/DLL)
  • XCVR interface clocks

For information about the preferred clock inputs connectivity to PLLs, DLLs, and global clock network, see the Packaging Pin Assignment Table (PPAT).

High-Speed I/O Clocks

High-speed I/O clock networks are driven by I/O or CCCs. The 
high-speed I/O clocks feed reference clock inputs of adjacent CCCs through hardwired connections.

CCC

The CCC is configured to have a PLL or DLL clock output, driving a high-speed I/O clock network.

Global Buffer (GB) is driven through the dedicated global I/O, CCC, or fabric (regular I/O) routing. The global network is composed of GBs to distribute low-skew clock signals or high-fanout nets.

A dedicated global I/O drives the GBs directly and are the primary source for connecting external clock inputs (to minimize the delay) to the internal global clock network.

For more information about global clock network, see PolarFire Family Clocking Resources User Guide .

Reset
For more information about DEVRST_N and user reset, see Reset.
DDR Interface
For more information about DDR routing and topology, see PolarFire Family Memory Controller User Guide .
Check Programming and Debugging Scheme.

For programming and debugging information, see Device Programming.

XCVR
For more information about XCVR, see PolarFire Family Transceiver User Guide .
See the bank location diagrams in the

PolarFire FPGA Packaging and Pin Descriptions User Guide to assess the preliminary placement of major components on PCB.

IOD
For I/O gearing interfaces, place the clocks and data based on the defined requirements by selecting the correct I/O. For more information about the placement of User I/O, see PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide .
See the information about implementing Generic IOD Interface in PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide .
See the Consolidated IOD Rules for pre-place and route guidance.